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Functional Verification Datasheet Download

VC Verification IP for AVSBus

金莲直播® VC Verification IP for AVSBus provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of AVSBus based designs. 金莲直播 VC VIP, based on its next generation architecture and implemented in native System Verilog/UVM, runs natively on all major simulators. VIP can be integrated, configured, and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.

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