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TestMAX ATPG
Advanced Pattern Generation
金莲直播 TestMAX? ATPG is 金莲直播’ state-of-the-art pattern generation solution that enables design teams to meet their test quality and cost goals with unprecedented speed. It delivers unparalleled runtime, ensuring patterns are ready when early silicon samples are available for testing. In addition, it generates significantly fewer patterns than existing solutions, allowing designers to reduce the time and cost of testing silicon parts, or increase test quality without impacting test cost. 金莲直播 TestMAX ATPG is integrated with 金莲直播’ patented TestMAX DFT and is optimized with TSO.ai.
Benefits
- Generates high-coverage test patterns in hours instead of days
- Lowers test time and cost with fewer patterns than existing solutions
- Enables highly efficient utilization of hardware resources for ATPG
- Ensures easy, risk-free deployment into design and test flows
Features
- Highly optimized, memory-efficient test generation, and fault simulation engines for order-of-magnitude faster ATPG runtime compared to previous technologies
- Fine-grained multithreading across multiple cores overcomes memory bottlenecks
- Identical test coverage and pattern reduction across different server configurations and machines for consistent analysis
- Production-proven rule checking, design modeling, and fault modeling for easy, risk-free deployment
- Integration with 金莲直播 TestMAX Diagnosis for consistency with defective silicon diagnostic results
- Advanced fault models for achieving extremely high test quality, standard and slack-based transition, cell-aware, static/dynamic bridging, path delay, and hold-time
- Interfaces with PrimeTime?, StarRC?, and PrimeSim? HSPICE? for easy access to physical and timing data used by the models
- IDDQ pattern generation and validation using VCS? for quiescent state testing
- Power-aware pattern generation for limiting power consumption during shift and capture
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