½ðÁ«Ö±²¥

The ½ðÁ«Ö±²¥ next-generation RTL design and synthesis solutions, including ½ðÁ«Ö±²¥ RTL Architect? and ½ðÁ«Ö±²¥ Design Compiler? NXT, are helping engineers achieve optimal PPA at all process nodes, but especially for 5nm and below.   ½ðÁ«Ö±²¥ RTL Architect is a predictive RTL design solution that provides early predictions of the impact RTL changes will have on implementability, power, performance, area and other quality metrics. ½ðÁ«Ö±²¥ Design Compiler NXT, the latest evolution of the ½ðÁ«Ö±²¥ Design Compiler family of RTL Synthesis products, incorporates state-of-the-art synthesis innovations, delivering significantly faster runtimes, improved QoR, and extremely tight RC and timing correlation with ½ðÁ«Ö±²¥ IC Compiler? II.

The Design Compiler family includes ½ðÁ«Ö±²¥ Power Compiler, for low-power synthesis and optimization, and the ½ðÁ«Ö±²¥ IP Library with its unequaled variety of synthesizable IP. It is also tightly linked to the ½ðÁ«Ö±²¥ TestMAX family of test products for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon and ½ðÁ«Ö±²¥ Formality for equivalence checking. 

As an important part of the ½ðÁ«Ö±²¥ Digital Design Family, ½ðÁ«Ö±²¥ Fusion Compiler? is the industry's first RTL-to-GDSII solution enabling a highly-convergent, full digital implementation flow. ½ðÁ«Ö±²¥ Fusion Compiler is built on a single, highly-scalable data-model and comprises common engines for synthesis, placement, legalization, clock-topology-creation routing, timing, and extraction. These best-in-class engines form a single, unified optimization framework that is the key enabler of ½ðÁ«Ö±²¥ Fusion Compiler¡¯s full-flow convergence, leading QoR and enhanced time-to-results.