金莲直播 Cloud
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金莲直播' StarRC? solution is the EDA industry’s gold standard for parasitic extraction. A key component of the 金莲直播 Digital Design Family , it provides a silicon accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal. memory IC and 3DIC designs. 金莲直播 StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows along with debugging capability delivers unmatched ease-of-use and productivity to speed design closure and signoff verification. 金莲直播 StarRC comes with in-built field solver Rapid3D?, which can serve as a reference or provide higher accuracy measurements. 2.5D and 3DIC extraction is also supported by 金莲直播 StarRC.
Key Benefits
Features
Tightly Integrated in Design Analysis Ecosystem
金莲直播 StarRC parasitic extraction solutions tight integration with industry standard digital and custom implementation systems, physical verification timing, signal integrity, power, thermal and circuit simulation flows deliver unmatched ease-of-use and productivity to speed design closure and signoff verification.?
- Learn more about 金莲直播?StarRC for custom design
- Learn more about 金莲直播 StarRC and the extraction continuum
- Learn More about the 金莲直播 Digital Design Family?